D43D System design for 3D silicon intergration Workshop
Friday June 27 2008

3-D ICs enable dramatically improved performances at a much lower cost compared with new leading-edge sub 32 nm transistor fabrication.
The success of these new ICs depends on the availability of new methodologies and skills that are required to achieve acceptable design quality and productivity.
This workshop brings together key actors from the semiconductor, system houses and design industry to build a vision of the next step in 3D integrated ICs design.

Topics addressed are:
Applications requiring 3D
Interconnect architectures and thermal management for 3D ICs
Application partitioning floor planning for 3D architectures
Modeling characterization and testing for 3D ICs.


Confirmed speakers:

Richard FERRAND, STMicroelectronics, France
Wilfried HAENSCH, IBM Yorktown, USA
Doris KEITEL SCHULZ,Qimonda, Germany
Didier LATTARD,CEA-LETI, France
Yusuf LEBLEBICCI, EPFL, Switzerland
Wan-Gyu LEE,NNFC, Korea
Lisa McILRATH, R3 Logic, USA

Fees:

Registration


Contact: ahmed.jerraya@cea.fr & marc.belleville@cea.fr