Workshop EC L2F (Electrical Characterization from Lab to Fab)
25 juin 2008

The increasing complexity of ultimate CMOS devices, and new semiconductor technologies, requires fast and accurate electrical characterizations either in R&D laboratories or for in line fabrication follow up. Therefore this workshop will widely consider the automated electrical measurements field.
The gate stack is a typical issue for advanced characterization and reliability development. The workshop will widen the discussion to measurement tools, throughput, and future technologies nodes.

Topics :
Semi conductor devices
Wafer level efficient and precise electrical characterization
Device parameters, reliability and variability issues
Automated tests capabilities and evolutions
Best practices exchanges between lab and fab requirements  

Organisateurs :
M. Brillouet, CEA Leti-Minatec
In partnership with Keithley instruments

Programme:
Chairman : F. Boulanger
O. Demolliens (CEA Leti-Minatec) - Opening
G. Reimbold (CEA Leti-Minatec) - Gate Stack characterization issues for R&D
Lee Stauffer (Keithley US) - CV measurement challenges and answers
Paul Meyer (Keithley US) - Pulse IV and Gate Stack
E. Vincent (STmicroelectronics) - Gate oxide reliability
Paul Meyer (Keithey US) - High throughput reliability
Bernd Bischoff (Texas Instruments US)  - High Automated Parametric Test
F. Riva (Numonyx Italy) - Test from R&D to industry technology follow up
Michael Chao (Keithley US) - High Density Arrays in Parametric Test
Michel Brillouet (CEA Leti-Minatec) - Round table :
“Parametric Variability at 65 nm and below – yield limiter”

Possible Leti-Minatec characterisation labs visit after the workshop (please contact us)

Tarifs:

Inscriptions


Contact:
A. Toffoli - CEA Leti Minatec (Alain.Toffoli@cea.fr or son assistante : Estelle.brague@cea.fr)