Events

WORKSHOP IMAPS " SiP or SOC, a real paradigm" may 30th

"SiP or SOC, a real paradigm"

Due to performances reasons (electrical speed, thermal needs, reliability …), a need for a smaller size and weight of products , a better portability and cost constraints; the silicon integration and microelectronics packaging take now a prominent share at the level of electronic systems design decision. The system integration is not only made with the interconnection of discrete components on a printed circuit board but it may drive to a real paradigm between the selection of a full silicon integration and a high densification of microelectronics packaging.

The recent progresses of microelectronics integration on silicon has lead to the development of highly customized function or system developed on a silicon die and mounted inside a standard package (BGA,CSP, etc…). This approach called System On a Chip or SOC is very well adapted to large series (ex. portable applications of consumer products, mobile phones …) and a lower cost. The major drawbacks of this approach are high design costs (complex IC design and costly tooling), a long time to market and possible intellectual property issues.

Another system approach is called System in a Package or SiP. The different functions of the system are implemented with different chips possibly using different technologies: standard bare silicon dies, microsystems, RF and passive components. These components are integrated in a single customized package, or an advance substrate. Easily, the SiP solution may use the advantages of a 3D approach, wafer level packaging as well. The advantages of SiP are medium development costs, a shorter time to market, the possibility to mix different silicon technologies. SiP is well adapted to small and medium series. Principal drawback is the cost for assembly (large volume applications).

The IMAPS workshop will review the latest R&D and manufacturing status of these solutions.


Registration

Programme:

mai 30th
9.45 -10.15	Opening Session B.Braux, Présidente IMAPS France Gi. Poupon, CEA LETI
10.15 -10.45	The revolution of System in Package : Technology, Design, Supply chain C. Cognetti, ST Microelectronics
10.45 -11.15	SIP poses new EMC challenges JM Yannou, Philips
11.15 -.11.45	Material Challenges and Solutions for Reliable System-in-Package design E. Rochard, Freescale C. Trigas, Freescale
11.45 -12.15	System-in-Package (SiP): An Alternative to System-on-Chip (Soc) R. Plieninger, Infineon Technologies

More information : www.imapsfrance.org
Contact: imaps.france@imapsfrance.org
Registration